Conventionally for electrical connection established between a chip and an external component in a semiconductor package by using wire-bonding technology, the quality of electrical connection and the distribution density of bonding wires are key factors to determine the reliability and performances of the semiconductor package. Therefore, it has become an important issue in the semiconductor industries to maintain relatively higher reliability of the bonding wires in wire-bonding and other fabrication processes.
A conventional semiconductor package fabricated using the wire-bonding technology is shown in FIG. 7. In the case of having a lead frame 50 as a chip carrier, a semiconductor chip 53 is mounted on a die pad 51 of the lead frame 50. A plurality of bonding wires 54 are bonded to bond pads 55 on an active surface of the chip 53 and to leads 52 of the lead frame 50, such that the chip 53 is electrically connected to the leads 52 via the bonding wires 54. Further, an encapsulant 56 is formed to encapsulate the chip 53 and the bonding wires 54 to completely fabricate the semiconductor package. According to the steps of the fabrication processes, it is realized that to improve the electrical quality of the bonding wires 54, not only the reliability of the wire-bonding process should be enhanced, but also the following encapsulation process plays an important role in determining the electrical quality of the bonding wires 54 so as not to degrade the bonding wires 54 during injection or filling of the encapsulant 56.
FIG. 8 shows the encapsulation process for the above wire-bonded semiconductor package. The lead frame 50 is placed between an upper mold 60 and a lower mold 61, wherein the chip 53 and the plurality of bonding wires 54 on the lead frame 50 are received in an upper mold cavity 62 formed between the upper mold 60 and the lead frame 50. The upper mold cavity 62 is communicative with a lower mold cavity 63 via gaps between the die pad 51 and the leads 52 and between the adjacent leads 52. A resin for fabricating the encapsulant 65 is injected through a gate 64 located at one side of the upper mold 60 or the lower mold 61, allowing the resin to gradually fill the upper mold cavity 62 and the lower mold cavity 63 and encapsulate the chip 53 and the bonding wires 54. However, referring to a top view of FIG. 9A, the plurality of bonding wires 54 around the chip 53 are arranged in various directions, such that a direction of the resin flow (as indicated by the arrows) would be perpendicular to that of some of the bonding wires 54. These wires 54 are thus subject to impact from the resin flow and incurred with wire sweep as shown in FIG. 9B, and the swept wires 54 may come into contact with adjacent wires 54 thereby causing short circuit and degrading the electrical quality. Particularly, the wire sweep more easily occurs for the longer wires having higher wire loops. Further, in order to improve the functionality and performance of semiconductor devices, the technology has been developed to incorporate more bonding wires and reduce a pitch between adjacent wires in the semiconductor devices. This adversely increases the occurrence of short circuit caused by undesirable contact between the adjacent densely-arranged wires.
In order to eliminate the above drawbacks, U.S. Pat. No. 5,359,227 discloses the use of bonding wires having different heights of wire loops as shown in FIG. 10. The wire loops of adjacent wires 75, 76 are made different in height, such that a pitch between the adjacent wires 75, 76 is increased by a height difference H of the wire loops of the wires 75, 76. This is to prevent the adjacent wires 75, 76 from contact with each other in the case of the wires 75, 76 being swept by the resin flow impact, thereby solving the foregoing electrical problem. However, this arrangement makes the largest loop height S of the wire 75 much greater than the original loop height (S-H) and the thickness of a chip 77, such that the overall package thickness would be undesirably increased, which not complies with the requirement of miniaturization in package size and also leads to increase in the fabrication cost on the mold and the encapsulation process.
Alternatively, U.S. Pat. No. 5,156,323 discloses a wire-bonding method using a capillary of a wire bonder to adjust its moving track to form a wire 85 with a predetermined shape of wire loop as shown in FIG. 11, so as to reinforce rigidity of the wire 85 and reduce the chance of wire sweep caused by the resin flow impact. However, this method only alters the loop shape of the wire 85 but not the pitch between the wire 85 and an adjacent wire. As a result, if the resin flow impact is great enough, the wire 85 would still be swept or shifted to come into contact with the adjacent wire thereby leading to short circuit and decreasing the production yield. Further, U.S. Pat. No. 5,111,989 similarly discloses a wire-bonding method to control the shape of a wire loop, which however encounters the same drawbacks as U.S. Pat. No. 5,156,323 and is not able to solve the foregoing problems.
Therefore, the problem to be solved here is to provide an improved wire-bonding method and a semiconductor package using this method, which can prevent adjacent bonding wires from contact and short circuit with each other due to resin flow impact, as well as provide advantages such as a miniaturized profile, simple fabrication processes and a high yield for the semiconductor package.